Hardware Memory Acceleration – what can you do better
November 8 @ 7:00 pm - 10:00 pm
Memory which allows addressing any byte and receiving as much data, related to that byte, as the bus allows.
If we had such memory before, we would not have any problems with different-word-width devices sharing the same bus, 32-bit instructions could be easily intermixed with 64-bit ones (and 16-bit ones, and any N*8-bit ones); caches would be optimal; and no useless bytes, summing up to Tbytes, would be shoveled around.
The same idea allows presenting data from non-sequential areas of memory on a bus in a unified word by addressing only a single byte. This is important in image analysis. With no hassle, you receive a pixel and all its surroundings via only one memory access. (No shift-registers)